Hierarchical Test Generation for Digital Systems Based on Combining Bottom-Up and Top-Down Approaches

A hierarchical test generation approach for digital systems which uses register-transfer (RT) and gate level system descriptions is presented. Decision diagrams are exploited as a uniform model for describing systems at different representation levels. The method combines bottom-up and top-down approaches to make hierarchical test generation more efficient by a synergism of deterministic and random low level techniques. It combines register transfer level deterministic test planning with gate-level local test generation based on deterministic approach at the bottom-up working mode and pseudorandom approach at the top-town working mode. Experimental results of using both modes of test generation are included which show high efficiency of the presented hybrid approach to test generation for sequential digital systems.